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ADE7518
WATCHDOG TIMER
The watchdog timer generates a device reset or interrupt within
a reasonable amount of time if the ADE7518 enters an erroneous
state, possibly due to a programming error or electrical noise. The
watchdog is enabled by default with a timeout of two seconds and
creates a system reset if not cleared within two seconds. The
watchdog function can be disabled by clearing the watchdog
enable bit (WDE) in the Watchdog Timer SFR (WDCON, 0xC0).
The watchdog circuit generates a system reset or interrupt (WDS)
if the user program fails to set the WDE bit within a predeter-
mined amount of time (set by PRE[3:0]). The watchdog timer is
clocked from the 32.768 kHz external crystal connected between
the XTAL1 and XTAL2 pins.
The WDCON SFR can be written only by user software if the
double write sequence described in the Writing to the Watchdog
Timer SFR (WDCON, 0xC0) section is initiated on every write
access to the WDCON SFR.
To prevent any code from inadvertently disabling the watchdog,
a watchdog protection can be activated. This watchdog protection
locks in the watchdog enable and event settings so that they cannot
be changed by user code. The protection is activated by clearing
a watchdog protection bit in the flash memory. The watchdog
protection bit is the most significant bit at Address 0x3FFA of
the flash memory. When this bit is cleared, the WDIR bit is forced
to 0, and the WDE bit is forced to 1. Note that the sequence for
configuring the flash protection bits must be followed to modify
the watchdog protection bit at Address 0x3FFA (see the Protecting
the Flash Memory section).
Table 65. Watchdog Timer SFR (WDCON, 0xC0)
Bit
7 to 4
Address
0xC7 to
Mnemonic
PRE[3:0]
Default
7
Description
Watchdog Prescaler. In normal mode, the 16-bit watchdog timer is clocked by the input
0xC4
clock (32.768 kHz). The PREx bits set which of the upper bits of the counter are used as the
watchdog output, as follows:
t WATCHDOG = 2 PRE ×
2 9
XTAL 1
PRE[3:0] Result (Watchdog Timeout)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010 to 1111
15.6 ms
31.2 ms
62.5 ms
125 ms
250 ms
500 ms
1 sec
2 sec
0 sec, automatic reset
0 sec, serial download reset
Not a valid selection
3
0xC3
WDIR
0
Watchdog Interrupt Response Bit. When cleared, the watchdog generates a system reset
when the watchdog timeout period has expired. When set, the watchdog generates an
interrupt when the watchdog timeout period has expired.
2
0xC2
WDS
0
Watchdog Status Bit. This bit is set to indicate that a watchdog timeout has occurred. It is
cleared by writing a 0 or by an external hardware reset. A watchdog reset does not clear
WDS; therefore, it can be used to distinguish between a watchdog reset and a hardware
reset from the RESET pin.
1
0xC1
WDE
1
Watchdog Enable Bit. When set, this bit enables the watchdog and clears its counter. The
watchdog counter is subsequently cleared again whenever WDE is set. If the watchdog is
not cleared within its selected timeout period, it generates a system reset or watchdog
interrupt, depending on the WDIR bit.
0
0xC0
WDWR
0
Watchdog Write Enable Bit. See the Writing to the Watchdog Timer SFR (WDCON, 0xC0)
section.
Rev. 0 | Page 79 of 128
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